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Naohiko Shimizu, School of Information Technology and Electronics, Tokai Univ.: My80, an i8080A instruction compatible processor, implemented in an Altera EPF10K30 or a FLEX EPF6016.
Bob Garrett and Martin Won, Altera:
PLD solution takes on microcontroller. I take this to be a marketing response to MicroBlaze.
"To accommodate both 16- and 32-bit data paths, we chose a 16-bit
instruction set, which would lead to a smaller memory footprint and also
aligned with the broader availability of low-cost 16-bit flash memories
for boot code. This choice also required only one memory access per
instruction for both 16- and 32-bit data path implementations of the
Nios processor, whereas a 32-bit instruction set would have required
two accesses per instruction in a 16-bit data path implementation."
That's the same thinking we used for xr16/xr32 and gr0040/gr0050.
You can also make a pretty good argument for a
24-bit instruction word architecture.
"We wanted the Nios processor to be perceived as a mainstream processor
architecture and not a toy for hobbyists. To avoid this type of confusion,
we added several sophisticated processor features including a large
windowed register file for fast context switching, an integrated and
vectored interrupt controller and dynamic bus sizing to accommodate
memories that are narrower than the processor data path."
Spin. Altera devices do not implement Xilinx's patented LUT
RAM feature, and so as I first discussed in Flex10K CPUs and
Flex10KE CPUs, because it is impractical to build
a small, fast fixed-size register file out of raw flip-flops and muxes,
you have little choice but to put register files in block RAMs.
In contrast, block-RAM-based windowed, multi-context, and vectored
register file options are available to both Xilinx and Altera.
To date, both Gray Research and Xilinx have chosen to use small
fixed-sized register files, presumably for high clock frequency performance.
(Certain windowed and multi-context reg file schemes are interesting
in avoiding activation record and context switch memory traffic, though.)
Embedded block RAM is just not as fast (and in many cases
can be more profitably used for other things, like an I-cache).
See also Using block RAM.
As for an interrupt controller, as discussed in the Circuit Cellar articles, in a flexible
soft CPU core, it is not necessary to fix a specific interrupt discipline:
"These artifacts of the fixed-pinout era not be hardwired into our FPGA CPU."
And the first FPGA CPU with dynamic bus sizing (to our knowledge) was the 1995
a pipelined 32-bit RISC with an 8/16/32-bit peripheral bus on chip,
in an XC4010, which was implemented by a hobbyist.
See also SoC On-Chip Buses.
Speaking for the community of "toy hobbyist" CPU designers, if I were
designing a cost-sensitive embedded system, I'd rather embed
a high-clock frequency 180 LUT/0 BRAM 16-bit RISC (or
a 270 LUT/0 BRAM 32-bit RISC), than a 1100 LE/several EAB 16-bit RISC
(or 1700 LE/several EAB 32-bit RISC).
The article is also interesting because (for the first time?) it publicly
discloses some features of the Nios instruction set.
For instance, we learn that Altera adopts a kind of long-literal
immediate prefix instruction, just as our xr and gr families do.
Altera, when will you openly publish
the Nios instruction set architecture specification?
Xilinx, when will you openly publish
the MicroBlaze instruction set architecture specification?
The Altera Nios programmer's reference manual is now available online
(12 MB PDF). Thanks to one of our readers for pointing that out.
Nick Tredennick, DynamicSilicon:
The Death of the DSP;
Embedded Systems and the Microprocessor -- Beginnings of the Long Downhill for the Microprocessor.
appears to be an extremely fast FCCM network filer box, with
hardware acceleration of TCP/IP, NFS, FTP, file system, and fibrechannel
data transport, using "re-programmable gate arrays".
Silicon Server White paper: "all data movement within the SiliconServer
architecture is carried out in hardware".
George Gilder with Mary Collins, Gilder Technology Report: The Storewidth Warp:
"In the BlueArc box, which uses Altera devices, FPGAs perform functions
in the spatial domain, such as spatial data flow, that were previously
forced to conform to a temporal processor. Altera Apex FPGAs perform
all hardware data transport with mere hundreds of CPU MIPS (millions of
instructions per second) rather than the thousands consumed by software
inside of traditional servers. FPGAs give the Silicon Server a true
performance advantage, one that would not have been possible a year ago
and will continue to grow over time, as costs continue to decline."
New GPL'd FPGA DSP soft core
from the University of Valladolid (Spain). Santiago de Pablo writes:
"It's a 16-bit fixed-point DSP processor, with precission extended to
24 bits, that can operate (in simulations) at more than 40 MHz (10 MIPS,
10 MACS) on Xilinx Spartan-II FPGAs."
FPGA CPU News, Vol. 2, No. 5
Back issues: Vol. 2 (2001): Jan Feb Mar Apr; Vol. 1 (2000): Apr Aug Sep Oct Nov Dec.
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.