|
It's good to be back. Over the next few days we'll be catching up on
our news backlog.
John Cocke
[07/16/02] John Cocke, the father of RISC computing, died.
Obituaries:
IBM Research;
New York Times;
The Guardian.
John Cocke and Victoria Markstein, IBM J. R&D., 1990:
The Evolution of RISC Technology at IBM.
Bruce Shriver, IEEE Computer (1999):
Just Curious: An Interview
with John Cocke.
Xilinx embedded FPGA cores for IBM Blue Logic
[06/24/02]
Xilinx:
Announcement.
Press Release.
FAQ.
White paper.
IBM:
Cu-08 (cool: must read);
Embedded FPGA cores:
| "ASIC Equivalent Gates |
Size |
Total I/O |
| 10k |
3 mm² |
384 (192 inputs/192 outputs) |
| 20k |
5 mm² |
512 (256 inputs/256 outputs) |
| 40k |
7 mm² |
640 (320 inputs/320 outputs)" |
Xilinx announces they have developed and licensed an embedded FPGA
core technology to IBM for its Blue Logic ASIC customers.
Beginning in a year or so, these customers will have the opportunity
to design in one or more 10K, 20K, or 40K "marketing gate"
embedded Xilinx programmable logic array cores.
Anthony Cataldo, EE Times:
Hybrid architecture embeds Xilinx FPGA core ....
Gale Morrison, Electronic News:
Xilinx, IBM Tie The Knot.
Crista Souza, EBN:
IBM and Xilinx advance ASIC design.
Murray Disman, ChipCenter:
IBM to Embed Xilinx FPGAs in ASICs.
Flashback: Peter Clarke, EE Times (2001):
Xilinx, ASIC vendors talk licensing.
Details are sketchy, but here's my (non-ASIC-designer) take on all of this.
Back at DesignCon'01 there was an interesting panel
(see Cary Snyder's report) on the coming
hybridization of fixed and programmable logic platforms.
Today 'ASICs is ASICs' and 'FPGAs is FPGAs' and never (rarely) the
twain shall meet. ASICs have compelling advantages in size, speed, power,
and cost, particularly for high volume customers. FPGAs have compelling
advantages in flexibility, upgradability, and time to market,
and low NRE costs. Some FPGA based designs might as well
be half fixed logic. Some ASIC designs desparately need a little
programmable logic to accomodate new interfaces, emerging standards,
and to target new markets.
With fine geometry mask set costs reportedly in the million dollar
neighbourhood, it is very expensive to make changes to ASICs, or to offer
a product line spectrum of more specialized devices. And there is
sometimes little opportunity for ASIC/ASSP customers to differentiate
their products against other vendors who also use the same ASIC/ASSP.
So ASIC fab customers don't order as many, and as many variants,
of ASICs as they might otherwise do.
By adding some programmable logic to their portfolio of Blue Logic cores,
I surmise IBM Microelectronics hopes to make/keep their ASIC platform
offerings more cost-effectively-exploitable in more circumstances.
Xilinx is now targeting both ends of the hybrid fixed + programmable
logic spectrum. First, with Virtex-II Pro's IP Immersion, embedding
hard cores in an FPGA fabric. And now, embedding FPGA fabric(s) in
predominantly fixed logic ASIC designs.
Upside for Xilinx: a toe in the water of the embedded FPGA space.
It seems to me that if any threats to their programmable logic
franchise should arise from eFPGA competitors, they can then
respond from a position of strength and experience.
More significantly, Xilinx can further extend the price/performance curve
of programmable logic -- you can ship medium volume products 100% in
programmable logic, then when in high volume, flexibly move to a cheaper
IBM ASIC process while still retaining the flexibility of programmable
logic where necessary.
Whether this flexibility will allow Xilinx to sell more, or fewer,
pure FPGAs remains to be seen.
In any event, hypothetically speaking, it's better for Xilinx to lose
an FPGA sale to an ASIC with some Xilinx eFPGA, than to an ASIC with
a competitor's eFPGA.
This develpoment portends serious new competition for embedded
programmable logic vendors like
Adaptive Silicon
(partner
LSI Logic),
eASIC,
Leopard Logic,
and to a lesser extent, the configurable eDSP vendors
Elixent and
PACT.
Indeed, as Cataldo, Morrison, Souza, and Disman all note,
embedded programmable logic has yet to gain much traction in the industry.
Still this announcement (as losers are wont to rationalize)
Legitimizes the Concept,
which could be construed as good news for other companies in this space.
Perhaps some day we'll even see multi-hybrids: chips with hard logic,
LUT-based eFPGAs, and ALU-based eDSPs, multiple processors -- whatever
best fits the problem.
I wonder if Xilinx will offer a similar techology through UMC.
Final word on this business concept goes to Erik Cleage of Altera,
as quoted
in Electronic Times:
"... [ASIC companies] are properly recognizing the value proposition of
programmable logic but naively looking at embedding it. They are coming
at it from a position of ignorance. I think the ASIC companies tend to
be surprised by how complicated and difficult it is."'
With technical details sketchy -- let's engage in some pure speculation
One would expect this product to include one or more CoreConnect-family
bus bridges, bridging the ASIC's hard CoreConnect bus and the embedded
programmable logic fabric. In which case, it would make it easy to
exploit programmable-logic-based CoreConnect peripherals, coprocessors,
etc., in which Xilinx and its IP partners have already been investing.
Perhaps (pure speculation) there will also be an easy way, using
CoreConnect, for an embedded host processor to read and write vectors
of "eIOB" flip-flops in the eFPGA as I/O space, or memory mapped,
control registers (reminiscent of the XC6200).
As I wrote
this spring,
"I'd wager that over the next few years, IBM will gather considerably more
CoreConnect licensees, partners, tools, and more CoreConnect reusable IP,
based upon this Xilinx alliance, than they've seen in the whole history
of embedded PowerPC ASIC products."
When I wrote this I anticipated these hypothetical CoreConnect-compatible
cores would be born in programmable logic and then made available in HDL
form to IBM and its customers to be recast in hard logic ASIC cores -- but
with this announcement, many of these soft cores could (presumably)
also be directly reused in an embedded FPGA.
Besides some CoreConnect interface(s), the traditional IOB cells at the
periphery of the logic cell array may need to be replaced or augmented
by something else, for flexible interconnection to signals within the ASIC.
And perhaps there will be a way to bond out some dozens or hundreds of IOB
pins out of the embedded FPGA core, giving ASIC designers the great flexibility
and forgiveness of programmable I/O. If so, that would seem to
be a killer feature.
Besides CLBs (LUTs) and IOBs, presumably an eFPGA array would benefit
from DLLs/DCMs, some BRAMs, and therefore (if V-II based) some fixed
point multipliers. Wait, no, the Cataldo article above states:
"Xilinx's FPGA core is architecturally similar to its Virtex FPGA fabric,
but it has stripped out the embedded RAM in order to reduce the size
and power consumption."
Alas. BRAMs are so useful as SERDES FIFOs and other things.
Another killer feature, assuming bonded out programmable logic I/O, would
be V-II Pro's MGT (multigigabit/s transceiver) links.
These could streamline interfacing Blue Logic ASICs to a number of
gigabit networking interfaces.
But again, if the BRAMs have been deleted, then presumably the MGT links
(which themselves displaced certain BRAMs in the LCA) are out too.
If so, that's unfortunate. Surely Xilinx would want to make it
easy to interface Blue Logic ASICs/ASSPs to standalone Virtex-II Pro
FPGAs using MGTs. Thus I will not be surprised if Xilinx and IBM
eventually offer V-II Pro compatible MGT Blue Logic cores (either
embedded in the eFPGA fabric or as standalone cores).
The tools issues and the business issues would look to be as daunting
as any silicon design issues: Power and timing and clocking and signal
integrity between the hard and soft domains (perhaps less of an issue if you
use a standard CoreConnect bridge). A myriad design verification issues.
LCA manufacturing testing (a chore that Xilinx currently handles "at the
factory" on behalf of its FPGA customers) for one or more eFPGAs per ASIC.
(If you only test one or a few FPGA reconfigurations, then congratulations,
you've got an embedded EasyPath eFPGA :-))
Presumably the various manufacturing testing bitstreams have to be
downloaded on the tester just as with standalone FPGAs.
Configuration: in some cases it will make sense to load a default eFPGA
configuration bitstream from an embedded ROM (does Cu-08 do embedded FLASH?),
while retaining the flexibility to load it from an off-chip source.
Wacky far-out idea: a preconfigured yet reconfigurable eFPGA
(with default configuration automatically established at power up via
an appropriate configuration bit default-1/default-0 circuit design
across all configuration bits in the device) might be a more compact
implementation than a generic eFPGA plus and an embedded configuration ROM.
Business issues: how is Xilinx to be paid? Royalties per core per design?
Royalties per core per ASIC fabricated?
Finally, for the pure FPGA designers in the crowd, this development
may not have much immediate relevance.
But it may prove important to FPGA intellectual property (cores
and platforms) vendors who someday may discover a high volume
market for their wares.
(Advice: strive to find some way to charge per instance
rather than per design.)
|