FCCM: Acronym for field-programmable custom computing machine, a computing device in which programmable logic devices replace traditional general purpose processors, or fixed logic, in order to achieve superior performance or other capabilities. See also the FCCM Conference.

LIW: Acronym for long instruction word, an instruction set architecture which explicitly encodes several independent instructions, to be executed concurrently, in each "instruction word".

logic cell: A unit of FPGA "area" equivalent to one 4-input lookup table and one D flip-flop.

LUT: Acronym for lookup table. A small RAM (e.g. flip-flops with output multiplexer tree), usually 16 bits (sometimes 8 bits), that implements an arbitrary combinational logic function of 4 (respectively, 3) inputs. Often found with a number prefix that indicates precise number of inputs. Thus a 4-LUT is a 4-input (16 bit RAM) lookup table.

MIMD: Acronym for multiple instruction, multiple data. A parallel computer with multiple independent threads of control. Conventional symmetric multiprocessors are MIMD architectures.

RPM: Acronym for relatively placed macro. Xilinx specific. A group of device primitives to which RLOC= attributes have been applied, in order to constrain the placement of the group and thereby floorplan the group. For example, attributing a with RLOC=R0C0, b with RLOC=R0C0 and c with RLOC=R0C1 constrains a and b to be placed in the same CLB/slice and c to be placed in the adjacent slice in the next column. Wherever a, b, and c may be placed in the device, they'll be placed together.

SIMD: Acronym for single instruction, multiple data. A parallel computer with a single thread of control broadcast across the plurality of execution units. Example: Thinking Machines CM-1.

SoC: Acronym for system-on-a-chip, an integrated embedded computer system on a single chip. In the context of SRAM-based FPGAs, this usually discounts an external FPGA configuration ROM and external RAM.