Friday, April 7, 2000

I am pleased to announce the publication of my article series, Building a RISC System in an FPGA, in the March, April, and May 2000 issues of Circuit Cellar magazine. I present the design and implemention of the XSOC System-on-a-Chip, including the new xr16 pipelined RISC processor core, on-chip bus, bus/memory controller, and integrated peripherals (parallel port, bilevel VGA controller), all in a single Xilinx XC4005XL FPGA. The first, second, and third articles are now available (Acrobat format). The xr16 processor is accompanied by a port of the lcc4.1 retargetable C compiler, an assembler, simulator, and demos. The project documentation includes a Getting Started guide, processor specifications, and annotated schematics. The project can be built using Xilinx Foundation or Xilinx Student Edition, and runs on the XESS XS40 prototyping card. The XSOC/xr16 design is now provided as synthesizable Verilog source, as well as Foundation schematics.

FPGA CPU News, Vol. 1, No. 1
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.