FPGA CPU News of December 2000


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Monday, December 4, 2000
Xilinx: "Xilinx Files New Patent Case To Bar Infringing Altera Products From Entering The United States": "The Altera products covered by the ITC filing include all of the Flex, Apex and Acex families". Further information.

Murray Disman, ChipCenter: Xilinx Announces DSP Initiative.

"One of the more impressive benchmark comparisons is that for a Fast Fourier Transform (FFT). Virtex-II is rated at being able to implement a 1024 point FFT in less than 1usec while operating at 140MHz. This can be compared with 41usec for Virtex-E and 7.7usec for a fast DSP processor core. The DSP Processor would have to be run at 800MHz to execute the transform in 7.7usec."

Friday, December 1, 2000
Ken Chapman, Xilinx: The SRL16E: Part 1. Part 2. Good stuff. File it under The Knowledge.
"Use of this exciting mode can rapidly lead to cost saving of an order of magnitude. Although there are cases where the SRL16E may be used automatically to save silicon area, the SRL16E will appear most in designs that have been well engineered."
I've been busy. Late in November I finished the design of new processor, the gr0040, and a new version of the XSOC system-on-a-chip framework, and ported a C compiler, assembler, and simulator to it. I wrote up the whole thing as a synthesizable literate Verilog program, which is my paper for DesignCon 2001.

As I explained earlier,

"The goals are to provide a simple, fully embeddedable MCU, comparable to KCPSM but C programmable, and to advance the agenda of demystifying processor design and encouraging student and enthusiast experimentation. (In retrospect, the pipelining of xr16 is good for performance but detracts from its simplicity.)"

Here is the conference-draft of this paper, Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip (PDF). Abstract:

"This paper presents the complete design of a simple FPGA RISC processor core and system-on-a-chip in synthesizable Verilog. It defines a RISC instruction set architecture and then describes how to implement every part of the processor. Next, an interrupt facility is added. The second half of the paper describes the design and implementation of the system-on-a-chip -- on-chip RAM, peripheral bus, and peripherals. Throughout, FPGA-specific issues and optimizations are cited. The paper concludes with a comparison with other FPGA processor cores and a brief discussion of software tools issues."

The design is licensed under the XSOC License Agreement (LICENSE). This license, now version 1.1, was changed slightly to refer more generally to XSOC "copyrighted works" and not so specifically to the XSOC/xr16 Project that was described in the Circuit Cellar articles.

Please send your comments and suggestions.

Caveat: this design simulates running sample programs (even timer interrupts), and synthesizes and builds, but I have yet to run it in real hardware.

And I am thinking about changing the reset scheme back to async reset via GSR.

FPGA CPU News, Vol. 1, No. 6
Back issues: Nov, Oct, Sep, Aug, Apr.
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: May 17 2002