Newsgroups: comp.arch.fpga
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
Date: Wed, 8 Dec 1999 08:50:07 -0800

anonymous wrote in message <82lgam$gls$1@sunlight.pku.edu.cn>...
>Hi,
>I want to use a three-port(two reads and one write) asynchronous SRAM(or
>register file)
>in my ASIC design. As the first step, I hope to verify my logic using
>FPGA, but I'am not sure if some FPGA can provide this capability. If not,
>are there some methods to implement the same function, for example, using
>discrete SRAM device. Any information about multi-port SRAM in FPGA or ASIC
>would be very appreciated.

To my knowledge, there is no primitive device support for such a construct
in any commercial FPGA device.  In fact after musing aloud about such things
(3-ported and 4-ported SRAMs) a few years back I received a reply from a
commercial FPGA device architect praying that such things never come to
pass!

So you'll have to use 1-port or 2-port SRAMs.  For example, you can use:

* 1 1-port SRAM and do RRW accesses over 3 cycles

* 2 1-port SRAMs and do two RR access in one cycle and the W access in the
second cycle

* 1 2-port SRAM and do the one R access in one cycle and the RW access in
the second cycle,

* 1 2-port SRAM (like the Xilinx dual port select RAM) where you can do two
reads and one write per cycle assuming one of the read addresses is the
write address.

* 2 2-port SRAMs and do the two RR accessses and the W access in one cycle.

Note it may be possible to do read accesses in the first HALF cycle and the
write access in the second HALF cycle.  That's the way I build compact one
cycle 2R1W reg files from 2 1-port SRAMs.

See also these sources:

* http://www.deja.com/getdoc.xp?AN=491241651
* http://www.deja.com/getdoc.xp?AN=336757776&fmt=text (Altera vs Xilinx)
* http://www3.sympatico.ca/jsgray/homebrew.htm

Jan Gray

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Last updated: Feb 03 2001