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Subject: FPGA multiprocessors
Date: 02 Oct 1997 00:00:00 GMT
Newsgroups: comp.arch.fpga

This just in from our paper designs department: the XC4062XL and XC4085XL
are sooo big...

The J32 (www3.sympatico.ca/jsgray/homebrew.htm) (a 32-bit RISC in half a
XC4010) processor's datapath, if redesigned for XC4000XL, should fit nicely
in 16 rows by 8-9 columns of CLBs.  This got me thinking:

16x9	datapath
16x5	(guess) control logic
16x6	16-entry by 4-word-line instruction cache
16x2	page mode DRAM controller (also reqs. 40-50 IOBs)
----------------------------------
16x22	integrated 32-bit RISC processor (32-bit instructions)
8x22	integrated 16-bit RISC processor (16-bit instructions)

Assuming careful floorplanning, it should be possible to place six 32-bit
processor tiles, or twelve 16-bit processor tiles, in a single 56x56
XC4085XL with space left over for interprocessor interconnect.  Also the
number of processor tiles can be doubled if we eschew the I-cache and
simplify the microarchitecture -- though performance would greatly suffer.

Jan Gray