Newsgroups: alt.folklore.computers,comp.arch,comp.arch.fpga
Subject: Alto in an FPGA (was CPU's directly executing HLL's)
Date: Wed, 7 Jul 1999 10:22:19 -0700

Paul Wallich wrote in message ...
>It's a little amusing to note that the emulator, the thread executing the
user's
>program, was actually the lowest-priority thread. (Also amusing to
>think that Alto micromachine was something like 1600 gates -- you
>could build dozens of them on a single FPGA).

Perhaps, but if you count the register files and constant and microcode
memory it was much larger than 1600 gates.

A while back (around Alto's 25th anniversary) I briefly considered
implementing an Alto in a Xilinx XC4000 FPGA.  A 1979 era Alto processor,
*excluding microcode memory*, requires approximately 400 configurable logic
blocks (CLBs):

CLBs  What
----  ----
16    32x16-bit R registers
128   8x32x16-bit S registers  (1979 Alto)
(16    32x16-bit S registers (1974 Alto))
128   256x16-bit constant memory
64?   rest of datapath
64?   control
(4096  4096x32-bit microcode control memory)
----
~400 CLBs + lots of TBUFs (the 16-bit "processor bus" is driven by 9+
sources)

This would probably fill a 24x24 CLB Xilinx XCS30XL.  Perhaps you could
include processor and equivalent I/O controllers in an XCS40XL.

Now Xilinx has introduced their Virtex device family, which features 8+
256x16 dual port embedded SRAM blocks.  You could implement the S registers
in one block ram, the constant memory in another.  A 2KW subset of the 4KW
control memory would require 16 more, but would still fit in one of the
larger Virtex devices.

ref: Thacker et al, Alto: A Personal Computer, chapter 33 in Siewiorek et
al, Computer Structures: Principles and Examples, McGraw-Hill, 1982

BTW, you can theoretically build dozens of simple CPUs in a single FPGA: see
discussion thread at http://deja.com/getdoc.xp?AN=277216882 (XC4085XL) and
also http://deja.com/getdoc.xp?AN=444640841 (Virtex).

Jan Gray

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Last updated: Feb 03 2001