Subject: Re: Floorplanning Intro?
Date: 17 Jul 1998 00:00:00 GMT
Newsgroups: comp.arch.fpga

Ray Andraka wrote
> I can't say that I've seen any literature on the art of floorplanning.
>Unfortunately really good floorplanning is more of an art than a
>science.  That should not discourage the neophyte however, as even basic
>floorplanning can have dramatic results.  The goal is of course to place
>the logic in ways that make the routing easier, less congested and
>shorter.  As a starting point, you might let the tool do the place and
>route.  After it is finished, read the placed design into the floorplan
>tool and start looking for ways you can improve the layout.  The first
>thing you will probably notice is how awful the automatic placers really
>are.

Indeed.

Steven Schlosser wrote
> I'm looking for an introduction to floorplanning for FPGA
>designs.  Can anyone suggest a good reference?  I'm designing for a
>Xilinx 4028EX using Synplify and Xilinx M1.4.12 for NT.  Thanks!

While not a floorplanning cookbook, everyone should read the Xilinx App Note
"Improving XC4000 Design Performance" by Camilleri and Lockhard
(http://www.xilinx.com/xapp/xapp043.pdf).  A few years back I was quite
influenced by this concise overview of the issues you must consider to make
fast compact Xilinx FPGA designs.  FMAPs, pipelining, floorplanning, time
specs, are all discussed.  It's a little out of date now but still
worthwhile.  Also, study some of the Xilinx library schematics (ADD16,
etc.) -- lots of RLOC'd FMAPs and such.


Ah, but Mr. Schlosser is using HDL synthesis.  Oh dear.  While many folks
routinely floorplan using either schematics and/or netlist generators such
as PamDC (see http://www.research.digital.com/SRC/pamette/Software.html), is
anyone successfully floorplanning with synthesis tools?

Is there an HDL to netlist synthesis tool that either --
1) supports placement constraint attributes on register declarations and/or
on subexpressions? (not just pin-locking) or
2) uses systematic, repeatable names for generated elements of the
synthesized netlist, enabling external placement constraints?  (It is not
acceptable if a small change to the HDL source renames all the synthesized
stuff, invalidating the external floorplan or guide files.)

In lieu of these features, one approach would be to write and verify the
entire design in an HDL, then reimplement the significant datapath modules
using explicit instantiation and placement via schematics or netlist
generator.  You get quick design, simulation, synthesis (target other
devices), possibility of design reuse, *and* optimal use of FPGA resources
so you can use a smaller slower cheaper device.


I have been searching for this happy medium myself.  As I write on the
pleasures of designing processors and systems-on-chip in FPGAs, I want to
express the designs
1) in source code, that
2) can be simulated, and which
3) enables compilation to non-Xilinx devices, and
4) enables reuse of preexisting designs from other sources, and
5) uses device features as efficiently as does my netlist generator, e.g.
which permits floorplanning.

I'd like to use Verilog because of 1-4, anticipating a future Xilinx Student
Edition with Verilog -- but I'm not willing to sacrifice my
nice, half as large, twice as fast, quick-place-and-route datapaths!  Any
ideas?  Otherwise its going to be either a) 100% netlist generator
(sacrificing 3-4) or b) Verilog + datapaths reimiplemented via netlist
generator.

BTW, http://www3.sympatico.ca/jsgray/sld021.htm is an old example of a
floorplanned 32-bit RISC processor datapath in half an XC4010.

Jan Gray

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Last updated: Feb 03 2001